In recent years, advanced information processing has promoted penetration of devices such as word processors and personal computers into offices and homes. Especially, in recent devices, their display-screens become larger with higher definition in order to display more information. The higher the definition of the display screen becomes, the higher in speed a dot clock of a video signal becomes.
Generally, in these devices, characters are on-screen-displayed on the display screen for displaying, for example, setting of contrast and brightness of a display, or displaying volume and a channel for a television receiver.
Conventionally, a video display apparatus for the above on-screen display disclosed in Japanese Patent Laid-Open Publication No. 6-319077 (1994-319077) (hereinafter referred to as background art document) is widely known. FIG. 7 is a block diagram showing the structure of the conventional video display apparatus disclosed in this background art document.
In FIG. 7, the conventional video display apparatus includes a PLL circuit 101, an inverter (NOT) circuit 102, a logical multiplication (AND) circuit 103, a counter 104, a switching part 105, and a display unit 106.
The PLL circuit 101 receives a horizontal blanking signal (H-BLK) synchronized with a video signal, and generates a clock of a constant frequency according to H-BLK. Based on the clock generated by the PLL circuit 101, the counter 104 generates a Ys signal that provides a position of the first character of an on-screen signal (period for on-screen display) to control switching of the switching part 105. Following the control by the Ys signal outputted from the counter 104, the switching part 105 switches between the video signal and on-screen signal, and outputs the on-screen signal to the display unit 106 only during the period for on-screen display.
In general, such devices that selectively output the Ys signal and on-screen signal by receiving the synchronizing signal such as H-BLK are widely available on the market.
Also, as well known, if a dot clock speed of the received video signal is high, parallel processing in, for example, two-phases, are carried out to increase a speed for processing video signals by decreasing an input clock speed of a display driver.
As stated above, as the definition for various video signals becomes higher, display characters with higher definition are required for on-screen display. Therefore, the on-screen signal has to operate on a clock synchronized with the dot clock of the video signal.
However, actual on-screen display devices do not meet the above requirement. Also, even if the on-screen display device operates at a desired clock frequency, it is difficult for the on-screen display device to interface with a video display processing circuit for inserting the on-screen signal into the video signal. Moreover, when the on-screen signal is inserted into the video signal subjected to the above parallel processing, the resolution per character is decreased.
Therefore, an object of the present invention is to provide a video display apparatus and method capable of providing, even if an on-screen display device that operates only on a clock lower in speed than a dot clock synchronized with a video signal that is used, high-definition on-screen display based on the dot clock.